The CYBOT Sonar IO Board

HOW IT WORKS

The sonar processor UC2 generates a constant output to the ultrasonic transducers
This is present on pins 5 and 6 of the 13 pin connector

Both sounders seem to be connected together, in parallel, in phase.
This has been observed from the pictures available.

The output of pins 5 and 6 are complementary.
When pin 5 is at +5v, pin 6 is at 0v and vica-versa.
This allows for a greater peak-peak signal.



The top waveform represents a single output, giving a peak to peak output of 5v

The lower waveforms represent a complementary drive system.
Outputs 1 and 2 represent the output from the microcontroller to the piezo's.

When the combined output is observed, say with respect to output 2.
Firstly Output 1 is at +5v with respect to Output 2.
Next, Output 1 is at -5v with respect to Output 2.
This gives an overall peak to peak waveform of 10v.

This frequency has approx 25uS period ( t=12.5uS ), giving a frequency of 40KHz

One concern, during the no-transmit period, the outputs remain in a complementary state.
Pin 5 is 0v, pin 6 is 5v.
It is not good to keep the transducers in this state.
It is preferred to keep both at the same level.


The microcontroller outputs 8 pulses, each 12.5us width.
This gives a period of 25uS, giving an output frequency of 40KHz

This output is generated every 25ms, approx.



LOGIC ANALYSER CAPTURES






The above two images show my further findings regarding the Sonar IO Board.
The lower is a zoomed in version of the cross-over, ping burst and delay.

In both images, the top trace is pin 2, pin 3, pin 5 and pin 6 at the bottom.

Pins 5 and 6 clearly show the complementary push-pull transmitter drive.

I already had established that pins 5 and 6 where complementary push-pull drives.

Pins 2, 3 and 4 didn't really show any activity.

So I re-tested them with a 10k pull-up, this gave me the rest of the jigsaw.
Obviously, they're open collector type outputs.
Pins 2 and 3, as you can see from the images, are left / right input gating.
On the top image, you can see the alternate gating in relation to ultrasonic ping bursts.

On the zoom version, you can see:

• Both gating inputs go low just before the ping burst.
• I've not measured the delay, but it's approx 70uS before the input is enabled.
• This exact sequence repeats, but with the other input enable becoming active.

I had assumed:

The comparator is used to gate the left / right inputs to pin 4.
This probably will be 'OR'ed together at the output of the comparators, with a pull-up.
Pins 2 and 3 may be used to blank off the non-selected input.
This leaves pin 4 to be the input back to the microcontroller.



From the schematic, the assumptions where correct.
I'll be adding more info soon.

I thought that the system would be as above, a nasty amplification stage etc.
The blanking signal is also used to control the input signal, via the preset.
This is quite a nasty implementation really.

Also, notice the sizable capcitors on the +5v rail.
Seems that they may have had some noise problems.

Now I know that the response from UC2 to Processor 1 indicates distance.
The response is a single byte.
The upper nibble indicates one sides object distance, the lower nibble the other.

How the value of the nibble relates to real distance is unclear at the moment.
The motor response may just be relative to the differential of the nibbles.

Communication observations are available in the communications section